The present invention relates to complementary field effect transistors and in particular to a complementary field effect transistor which is integrated by connecting a p-channel field effect transistor and an n-channel field effect transistor and to using thin film semiconductors in a method of manufacture thereof.
A CMOS complementary field effect transistor, in which a p-channel MOSFET and an n-channel MOSFET are integrated on a single silicon substrate, is well known in the art. FIG. 2 shows this structure in which a n-type silicon substrate 11 is formed with a p-well layer 12 and in which n.sup.+ source and drain diffusion layers 13 are formed in the p-well layer whereas p.sup.+ source and drain diffusion layers 14 are formed in the other portion. This CMOS construction is frequently used in logical operation circuits, however, it is deficient in that it requires a large number of fabrication steps and has a resultant high fabrication cost. Thus, it is desired to manufacture a number of complementary field effect transistors simultaneously, from an inexpensive substrate of large area using a thin film transistor technique.
It is therefore an object of the present invention to provide a complementary field effect transistor formed from a semi-conductor thin film in order to overcome the aforementioned drawbacks of conventional transistor manufacturing techniques.